Interleaved, Successive Approximation, and Pipelined Sub-Ranging ADC models.
These models are typical of the architectures used for high speed analog to digital converters.
This is a 32 bit RISC based Pipelined Processor design.
The attached model implements a Sobel edge detection algorithm in Embedded MATLAB.
This demo shows how to read in an image operate on the serialized data and reconstruct the image back from serialized data after applying Sobel...
A LISP-like XML glue language with an XML syntax.Ideal for pipelined XML aggregation, transformations and filtering with accessors to a content repository.Embeddable Java implementation includes XSLT engine XT,servlet, command line and applet.
A MIPS processor modeled in Java for educational purposes and aimed at undergraduate Computer Architecture courses. It presently runs MIPS 32-bit R3000 ELF executables on any platform where Java itself will run. Five successively more...
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