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Cart2Cart: Veyton to OpenCart Migration 1.0
MainMedia Tiff Image & Fax ActiveX SDK 1.58
VISCOM Video Edit ActiveX Control 2.68
Cart2Cart: H.H.G. Multistore to OpenCart Migration 1.x
Mainmedia Screen Capture Directshow 1.38
Joyfax Broadcast 7.85.0815
Cart2Cart: AceShop to OpenCart Migration 1.x
Key Transformation 8.1115
Mainmedia iPod Encoder Directshow Filter 1.48
VISCOM Video Media Player ActiveX SDK 5.15
EntityDAC 1.1
Cart2Cart: Interspire to OpenCart Migration 1.x
Mainmedia TIFF Merge Split ActiveX Component 1.58
VISCOM Image Thumbnail ActiveX SDK 5.17
Cart2Cart: Shopp to OpenCart Migration 1.x
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OpenWire Studio Beta2
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Ruby-VPI is a Ruby interface to IEEE 1364-2005 Verilog VPI and a platform for unit testing, rapid prototyping, and systems integration of Verilog modules through Ruby. It lets you create complex Verilog test benches easily and wholly in Ruby.



AES is AlberT-EasySite / a powerfull Framework for easy generation of full-featured sites, with particuar attention to graphics, security and coding style. With this script you can, view an AES demo, browse into highlighted code of current AES...



Add AES encryption or PKI-enable your apps or websites. Chilkat Crypt allows applications or websites to encrypt/decrypt data or files using the latest AES symmetric encryption algorithms, including Rijndael, Twofish, and Blowfish. You can also...



PyCrypto-based authenticated encryption using AES-CBC and HMAC-SHA256. This class only supports shared secret encryption. Look elsewhere for public key encryption.



Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.



Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.



Avaya AES Bulk Administration tool. Allows adding and deleting of extensions in AES either by range (i.e. 4300-4352) or by using an comma-delimited file as a source.



AesLib.pas is a Delphi interface to the AES encryption routines fromBrian Gladman. Generating of a salt valuePassword verificationGenerating of authentication codeEncryption of a streamDecryption of a stream.The source code of a sample program is...



Powerful, reliable and flexible disk encryption program that lets you create encrypted disk partitions (drive letters) to protect your confidential information. Private Disk hides and restricts access to your programs and data. Dekart Private Disk...



HsCipherSDK is an Encryption Library providing an API to a suite of symmetric key cryptographic algorithms and one way hash digital signature algorithms. The library includes the following block and stream cipher modules:

* AES...



phpPassSafe is a web based Tool for secure, rolebased password storage and management. The passwords are stored aes-256 encrypted. Now a random password generator is included.



User AES-128 bit encryption in counter mode of operation. supports interactive mode of operation and command line mode of operation.



Win32 and Win64 DLL to encrypt strings or files with a very fast implementation of AES 256 bits and standard RC4, full Unicode support through utf-8 encode



ActiveX OCX to encrypt files with a very fast implementation of AES 256 bits and standard RC4, for news and improvements visit http://rspencdll.sourceforge.net/



Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications.



TextConverter is a graphical text editor allowing the user to encrypt/decrypt the textual contents displayed on the screen using a 128-bit AES (Advanced Encryption Standard) cipher.



SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.



This is a formal equivalence checking tool developed @ IIT Guwahati which can be used to verify functional equivalence between circuits (combinational and sequential) of the formats BLIF, verilog and EDIF.



FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output.

With...



Experimental ESL Compiler from C to Verilog