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Code 1-20 of 36   Pages: Go to  1  2  Next >>  page  

Numerical integration with Monte Carlo method (on FPGA chip).


- Matlab/Simulink
- Diamond IDE (3L)
- FPGA Xilinx VIrtex II (SMT8036E)
- Visual Studio (Optional)
- Xilinx System Generator (Recommended)
- Xilinx ISE (Recommended)

-ideal converter
-introduction o errors in both ADC and DAC stages (fluctuation and mismatch)
-scrambler function

Interleaved, Successive Approximation, and Pipelined Sub-Ranging ADC models.
These models are typical of the architectures used for high speed analog to digital converters.

Pinger for ADC/ADCS Hubs, Public Pinger for ADC/ADCS (Advanced Direct Connect / Secure ) Hubs written in PHP ( with Java hasher ) and it supports both ADC and ADCS protocols , TIGR and PING extensions.

A project to allow FPGA signal processing systems to be built in the same way that GNU Radio flow graphs are put together.

FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.

Advanced Direct Connect (ADC) is a simple protocol for a client/server-oriented messaging and file sharing system. The ADC Project aim to provide documentation for the ADC community and the developers.

Use xilinxbram.m and xilinxbraminit.m functions to generate VHDL or Verilog fraction of code to initialize Xilinx FPGA (Spartan, Virtex) 18k block RAM.
Recent revision is also available here:...

This code was written for a colleague of mine that needed a quick script that could convert a 16 color bmp to a Xilinx FPGA memory file. This could be used for your projects or for an example on the structure for your own coe files. Zip file...

Holds all information related to creating an Agile Development Methodology geared towards ASIC/FPGA Verification.

libgfpga is a light-wight C/C++ programming library to evaluate and discover FPGA configuration by different manufactures such as Xilinx or Altera. In the future I'm planning a backend for in system programming.

A fast VHDL compiler that will create the compiled bit stream for FPGA/CPLD electronic components. This compiled bit stream will be the bit stream that is uploaded to these electronic components OR into any simulation test bench.

This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.

This project is destinated to develop um sistem to make more easy projects to embebed sistems that uses FPGA or Microcontrolers, and the programation in many plataforms and languages. There is a IDE and a hardware system to develop some products.

-error calculation for DAC's finite bandwidth & slew-rate
-remedy to the error
-dynamic performance
-simulation with real binary resistive DAC
-description file

For a full description of the models, refer to the September 2007 MATLAB Digest article.

We present a series of Simulink models to design a high-level behavioral...

This could be very useful model when used in signal processing. I have implemented this to filter the disturbances in my ADC signals in my programming and it works good.

This package is a continues to be expanded. New examples include: VCO with user defined phase noise, impedance matching and filter design, interleaved ADC, clock multiplying delay lock loop, clock recovery for NRZ data. Further examples include:...

This set of models elaborates a simple "system level" descrition of a GPS receiver channel all the way to operating hardware. Real world captured GPS signals are used to test the initial receiver design. Ultimatly, the design is...

Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.